1. Field of the Invention
The present invention relates to a pattern evaluating system for evaluating a local pattern whose process margin is small on a LSI chip and more specifically to an evaluation object pattern determining apparatus for determining the local pattern to be evaluated. Still more, the invention relates to an evaluation object pattern determining method for determining the local pattern to be evaluated and an evaluation object pattern determining program for causing a computer to determine the local pattern to be evaluated.
2. Description of Related Art
With the advancing miniaturization of patterns of LSI chips, such patterns as having a line width even less than a wavelength of exposure light have been created and a super-resolution technology such as an optical proximity correction has been introduced in manufacturing semiconductor devices such as the LSI chips. However, it is still difficult to completely remove inclination (slack) of sidewalls or roundness of corners of the pattern of the LSI chip even by the super-resolution technology and it is important to fully evaluate the pattern after forming it. There has been known a method of evaluating such patterns by using CAD (Computer Aided Design) data as a method for evaluating the patterns formed on a wafer as disclosed in Japanese Patent Application Laid-Open No. 2004-228394 for example.
JP 2004-228394A discloses that it comprises a means for determining position (coordinates) of a pattern to be evaluated by employing the CAD data, an image acquiring means for acquiring an electron beam image of the actual pattern at the position determined as described above, a means for picking out a white band that corresponds to an edge portion of the actual pattern from the electron beam image and a means for evaluating a geometry of the pattern by superimposing the white band with the CAD data. JP 2004-228394A describes that it is capable of detecting changes of focus and aberration of an exposing apparatus because it can evaluate changes of the geometry of the pattern by such indices as a displacement, an expansion and/or shrinkage and a deformation volume of the pattern.
Heretofore, local patterns having a small process margin have been picked out of a wide range pattern of a LSI chip by way of simulation as described in JP 2004-228394A to determine the position (coordinates) of the pattern to be evaluated by using the CAD data. However, it has been considered that it takes an enormous amount of time to evaluate the all local patterns in manufacturing the LSI chips and in a mass-production stage in particular because there is a case when a number of the picked out local patterns becomes enormous. Meanwhile, although it is required to evaluate the all local patterns to be evaluated in the mass-production stage of the LSI chips, there is a case when the local patterns to be evaluated are not contained in the local patterns picked out by way of the simulation. Thus, there have been the cases when the number of the local patterns to be evaluated is excessive or insufficient.
It has become clear that the local patterns that are not necessary to be evaluated are contained in fabricating the LSI chips and in the mass-production stage in particular when all of the local patterns were evaluated and studied. It is possible to shorten the evaluation time and to have a temporal margin of adding omitted local patterns in the evaluation by skipping the evaluation of those local patterns unnecessary to be evaluated. Thus, the evaluation may be carried out efficiently.